As a semiconductor device is miniaturized, the importance of measurement and inspection using a scanning electron microscope (SEM) capable of visualizing a pattern having a width of a nanometer order has increased. In PTL 1, described is an evaluation method in which surface irregularity formed on a pattern side wall is evaluated by using a signal obtained by the SEM. The surface irregularity is referred to as line edge roughness (LER) or line width roughness (LWR). Since roughness has an influence on a characteristic of a circuit formed on a semiconductor device, it is required to appropriately perform an evaluation.
Further, in PTL 2, described is a method in which a plurality of times of measurement is performed based upon a plurality of times of beam scanning, and simultaneously, a line width before shrinkage (before beam irradiation) is estimated by extrapolation, so as to accurately measure a line width of a pattern formed by a material which is shrunk by irradiation of an electron beam such as an ArF resist.